SYMATICSGen1 validates.
Gen2 produces.
A two-generation path from FPGA proof-of-concept to production silicon. Gen1 closes the architecture on a 64-chip domain. Gen2 scales to production MoE, long-context, and agentic workloads.
Gen1 — Architecture Validation
Goal: prove the core principles of state-resident structural computing on real hardware — before any tape-out commitment. We report what is done, what is in progress, and what is next. Nothing below is a silicon measurement.
Done
- Gen1 architecture defined: compute array, state domain, and fabric topology
- Design partners engaged for front-end (Taiwan) and implementation (Canada)
- FPGA platform selected: AMD Alveo V80 compute nodes, AMD Versal VPK120 fabric node
In progress
- Architecture specification and cycle-level C-model
- Multi-node FPGA proof-of-concept: compute and fabric nodes in build
- Proof-of-concept compiler for compile-time state-path scheduling
- Singapore concept launch, 5–7 Nov 2026 (architecture exhibit, no live compute)
Next
- FPGA build completes end of Nov 2026; first results (fixed-latency state transfer) published as measured
- Published measurements of latency determinism and state residency
- Scaling toward a full 64-chip domain equivalent and broader workload characterization
Gen1 closes the architecture. Gen2 moves to production silicon.
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SIF-Link: keep the PHY, delete the rest
SIF-Link keeps the physical layer (SerDes, alignment, CRC) and reuses mature commercial IP. Everything whose job is to manage unpredictable traffic — routing, flow control, QoS, CXL transactions — is deleted and replaced by compile-time configuration.
Determinism by design
SIF traffic has no unpredictability by construction: single-source per slot, fixed fanout, compiler-scheduled. No mechanism is needed to manage what doesn't exist. Latency equals pure pipe depth — no queueing term.