SYMATICSGen1 validates.
Gen2 produces.
A two-generation path from FPGA proof-of-concept to production silicon. Gen1 closes the architecture on a 64-chip domain. Gen2 scales to production MoE, long-context, and agentic workloads.
Gen1 vs Gen2
A two-generation path with clear risk closure at each stage before commitment to the next.
| CAPABILITY | GEN1 | GEN2 |
|---|---|---|
| Ingress efficiency | ~45% | ~90%+ |
| CSL function | Deterministic memory ingress block | Prefetch, reorder, compression, bandwidth shaping, multi-domain scheduling |
| SIF form | FPGA prototype (reduced-scale hub) | Dedicated fan-out ASIC (full 64-port hub) |
| Hub lane rate | ≥10 Gbps (FPGA SerDes) | 16 Gbps / 32 Gbps headroom |
| Target workload | 64-chip domain validation | Production MoE, long-context, agentic |
| Scale-out | Physical channels reserved | Enabled: structure extension + multi-domain scheduling |
| RAS strategy | CRC + phase restart | Full RAS after link-retry vs. restart decision |
Validation phases
Each phase closes a specific risk before tape-out commitment.
SIF FPGA
Map a reduced-scale single hub on FPGA. Measure source-to-hub-to-receiver broadcast latency against the sub-200 nanosecond target. Verify source order preservation. Prove the inter-domain direct link.
- ✓FPGA hub platform (8–16 MPU scale)
- ✓Latency measurement vs. <200 ns target
- ✓Source order preservation proven
- ✓SerDes IP evaluation + link sim
CSL Ingress
Close the weight-loading loop: DDR to CSL prefetch to MPU Column State Ingress, column by column. Verify ingress rhythm matches compute rhythm. Begin rack physical design.
- ✓Single cluster (4-chip) ingress closed
- ✓Compute-ingress cadence match proven
- ✓Cold plate / rack physical design
- ✓Power delivery characterization
System Integration
Integrate on-chip compute, SIF traverse, and CSL ingress into a closed loop. 64-chip domain bring-up: ~25 kW rack, liquid cooling, complete management and telemetry stack.
- ✓64-chip domain bring-up
- ✓~25 kW rack operational
- ✓Full management + telemetry
- ✓RAS validation (CRC + restart)
SIF-Link: keep the PHY, delete the rest
SIF-Link keeps the physical layer (SerDes, alignment, CRC) and reuses mature commercial IP. Everything whose job is to manage unpredictable traffic — routing, flow control, QoS, CXL transactions — is deleted and replaced by compile-time configuration.
Determinism by design
SIF traffic has no unpredictability by construction: single-source per slot, fixed fanout, compiler-scheduled. No mechanism is needed to manage what doesn't exist. Latency equals pure pipe depth — no queueing term.