Render of a concrete wall with a lit path of blue cells climbing across it

Events

Meet the Symatics team in Singapore this November.

SYMATICS is investigating a purpose-built architecture for stateful and reasoning-intensive AI workloads. This November we are presenting the architecture in Singapore — first as a public exhibit at AI for Good Summit, then in a closed-door briefing for technical leaders, partners and investors at NTU.

Exhibit — 5–7 Nov NTU briefing — 8 Nov

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AI for Good Summit — exhibit

5–7 November 2026 · Shangri-La, Singapore

Visit the Symatics exhibit at the AI for Good Summit and follow the state path across it — MPU → SIF → fiber → MPU — the route state takes between nodes in our scale-out architecture. A fiber-spool control lengthens the link segment, and a fault button shows how the next epoch recovers clean.

Scale-out architecture exhibit · Singapore concept launch

What the exhibit shows, and what it isn’t →

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Closed-door briefing at NTU

Sunday 8 November 2026 · 2–5 PM · NTU One North, Level 7 · By invitation

A boardroom-quality session on architecture, validation, AI economics and roadmap — with Q&A and investor follow-up scheduling. Designed for technical leaders, partners and investors evaluating stateful AI infrastructure.

Request to join

Symatics booth concept render: rack-scale state domain, demo screen and fiber-spool table — Exhibit concept render · AI for Good Summit booth

Where we are

An evidence-building programme — measured, then published.

The exhibit visualises the architecture we are validating. Our architecture simulation and validation POC completes end of October 2026, and the multi-node FPGA proof-of-concept build is targeted for end of November 2026. Results will be published on the roadmap as they are measured.

Done

Architecture specification.
Cycle-level model with design partners.
Exhibit design for Singapore.

Now → Next

Architecture simulation & validation POC — completing end of October 2026.
FPGA proof-of-concept build — end of November 2026.
Results published here as they are measured.

FPGA-based validation platform — not a finished commercial product · Architecture targets for illustration only · Gen1 silicon planned for 2028