SYMATICS
One state domain, made visible.
A rack-scale exhibit of a Symatics state domain. A pulse of light traces the path state takes between compute nodes: out of one node, through the fabric, across an optical link, and into the next node — at a fixed cadence, on the same path, for the same duration, every cycle. That repeatability is the architecture's core claim.
Two controls on the table let you test it yourself.
Change the fiber length
Switch the optical spool from 10 m to 500 m. Only the link segment stretches, by the amount the length predicts. Nothing else in the schedule moves — latency is pipe depth, with no queueing term.
Press the fault button
A corrupted transfer is flagged at its destination and dropped: fail loud, no retry, no hidden recovery traffic. The next cycle runs clean.
Ask the architects
The founding team is at the booth to walk through the architecture, the Gen1 plan, and where the MPU fits.
Where this fits. The exhibit presents the architecture at system level and quotes no performance numbers. Our architecture simulation and validation POC completes end of October 2026, with the multi-node FPGA proof-of-concept build targeted for end of November 2026; we will publish results on the roadmap as they are measured.
5–7 November, Shangri-La Singapore.
Our leadership team is in Singapore for the AI for Good Summit and the Alliance for Good Business & Philanthropy Forum. We are setting up 1:1 meetings with investors, ecosystem and silicon partners, research groups, and senior engineers.